gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 1 1 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 1 features ? robust gan protection at any power up/power down sequence ? fixed gate with pulsed drain bias voltage. add - on module allows for gate pulsing ? open drain output current of 200 ma for external mosfet switch drive ? 30 db typical emi/rfi rejection at all i/o ports ? 6.60 x 22.48 mm 2 package with 1 mm pitch smt leads ? target 500 ns total switch transition time ? low power dissipation < 100 mw ? gate bias output current 50 ma for heavy rf compression ? rohs* compliant and 260c reflow compatible description the mabc - 001000 - dps00l is a low power dissipation bias controller that provides proper gate voltage and pulsed drain voltage biasing for a device under test (dut). applicable duts include depletion - mode gan (gallium nitride) or gaas (gallium arsenide) power amplifiers or hemt devices. the module also provides bias sequencing so that pulsed drain voltage cannot be applied to a dut unless the negative gate bias voltage is present. the applications section of this datasheet will show how the module can be implemented for the following two applications: ? application option 1: fixed negative gate biasing with pulsed drain biasing. ? application option 2: pulsed negative gate biasing with pulsed drain biasing. both of these application options will recommend the external circuitry and p - channel power mosfet. the mabc - 001000 - dp000l module can also be installed onto an mabc - 001000 - pb2ppr evaluation board for evaluation, test, and characterization purposes. ordering information part number packaging mabc - 001000 - dps00l tray mabc - 001000 - dps0tl tape & reel 2 mabc - 001000 - pb2ppr gate and drain pulsing evaluation board 3 * restrictions on hazardous substances, european union directive 2011/65/eu. pin no. label function 1 gfb gate voltage ( - ) feedback 2,6,8,10 nc no connection 3 gco gate voltage ( - ) control output 4 gci gate voltage ( - ) control input 5 vgs gate ( - ) supply voltage 7,13,14 gnd ground 9 swg driver output to mos switch gate 11 p4v +5 v v cc input 12 ens mos switch enable ttl pin configuration 1 2. reference application note m513 for reel size information. 3. specify eval. board configuration when ordering: application option 1 or 2. see applications section for option details. 1. this configuration is for fixed gate bias. unused package pins must be left open and not connected to ground. functional schematic 1 2 3 4 5 1 2 1 1 1 0 9 8 7 6 1 3 1 4 + - + - g f b n c g c o g c i v g s e n s p 4 v n c s w g n c n c g n d g n d g n d
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 2 2 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 2 electrical characteristics: t a = 25c absolute maximum ratings 4,5 recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage, positive 4.3 5 5.5 v i cc supply current, positive - 13 - ma v gs supply voltage, negative - 8 - 6 0 v i gs supply current, negative - - 3 - ma v enl input voltage, logic 0, pulse enable 0 0 0.3 v v enh input voltage, logic 1, pulse enable 2 3.3 4.3 v i en input current, pulse enable - 40 - ua v gth input, gate feedback threshold to v gs - 2.7 - v v dth input, drain feedback threshold - 65% swg - v v gc output voltage, pulsed/fixed gate - 8 - 3.5 0 v v gcr output voltage, pulsed/fixed gate ripple - 50 - mvp - p i gc output gate current, peak - 50 - ma r off output drive, open drain, off state v ds = 50 v temp. = +85c - 4m - ? r on output drive, open drain, on state - 1.2 - ? i on output drive, current, on state - 100 200 ma parameter typical supply (+) voltage, v cc +4.8 v to +5 v supply ( - ) voltage, v gs - 8 v to - 2 v logic voltage, ens, gse 0 v to +4.3 v analog ( - ) voltage, gci, gfb - 8 v to - 2 v switch driver sink current, swg - 1 ma to - 200 ma operating temperature - 40c to +85c parameter absolute maximum supply (+) voltage, v cc +4.3 v to +5.5 v supply ( - ) voltage, v gs - 10 v to 0 v logic voltage, ens, gse - 0.3 v to +4.5 v analog ( - ) voltage, gci, gfb - 10 v to 0 v switch driver voltage, swg 0 v to +60 v switch driver sink current, swg - 200 ma lead soldering temp (10 s) +260c operating temperature - 40c to +85c storage temperature - 65c to +150c 5. exceeding any one or combination of these limits may cause permanent damage to this device. 6. macom does not recommend sustained operation near these survivability limits.
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 3 3 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 3 timing diagrams symbol parameter conditions min typ max unit t d1 open drain on propagation delay 7 r pull - up = 700 ? v dd = 50 v i r = 71 ma avg. switch disconnected - 100 150 ns t d3 open drain off propagation delay 7 - 70 100 ns t rise1 open drain rise time 8 - 116 150 ns t fall1 open drain fall time 8 - 58 100 ns t d1 mos switch on propagation delay 7 - 200 - ns r load = 1200 ? v dd = 50 v i load = 42 ma avg. mos c iss = 760 pf r ds,on = 205 m? t d3 mos switch off propagation delay 7 - 1100 - ns t rise1 mos switch rise time 8 - 126 - ns t fall1 mos switch fall time 8 - 820 - ns t d2 gate bias on propagation delay 7 - 156 200 ns t d4 gate bias off propagation delay 7 - 148 200 ns t rise2 gate bias rise time 8 - 55 100 ns t fall2 gate bias fall time 8 - 44 100 ns 7. propagation delay is measured from 90% of the ttl signal to 10% of the signal of interest. 8. rise and fall times are measured between 10% and 90% of the steady state signal. timing characteristics: t a = 25c ens swg gco rf 9. q1 refers to an external p - channel mosfet that pulses the drain of the dut. see applications section for more information. vcc +5v external +5v to enable logic vdd (q1) 9 ttl vds vgs rf +5v +50v -3v -8v 0 0 90% pulse enable for t d1 d2 d3 d4 rise1 fall1 t t t t t fall2 t 10% 90% 10% rise2 t 10% 90% 90% 10% 0 +50v vod gate & drain switch open drain output mosfet switch output pulsed gate output rf output
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 4 4 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 4 applications section functional description the mabc - 001000 - dps00l gan bias controller/ sequencer module circuitry provides proper sequencing and generation of the gate voltage and pulsed drain voltage for a device under test (dut). reference the product view and pin configuration table on page 1. the basic functions of the circuits within the module are described as follows: ? overhead voltages for the circuits within the mabc - 001000 - dps00l module pin 11 (p4v) is the +5v vcc input that supplies the positive voltage for the circuits within the module. pin 5 (vgs) is the gate ( - ) supply voltage that is also used to supply the negative voltage for the circuits within the module. ? negative gate voltage for the device under test (dut) a voltage follower op - amp circuit provides a low impedance output to pin 3 (gco) gate voltage ( - ) control output. pin 3 (gco) output is connected to the gate terminal of a dut as shown in figure 1 on page 5. the reference voltage for the voltage follower is provided by the pin 4 (gci) gate voltage ( - ) analog input. this input reference voltage is developed by an external potentiometer/ resistive divider circuit as shown in figure 1 on page 5. it is recommended to use the - 8 v to - 3 v voltage that is also applied to pin 5 (vgs). reference: the external potentiometer is adjusted to set the gate voltage pin 3 (gco) to the dut. alternative voltage inputs such as a temperature compensation circuit or a digital - to - analog (dac) converter could also be supplied to pin 4 (gci). ? pin 9 (swg) mos switch driver output an n - channel mosfet develops the pulsed signal (swg) to drive the resistive divider network for the gate of an external p - channel hexfet as shown in figure 1 on page 5. the input signal for the internal mosfet is provided by the output from the sequencing circuits. ? sequencing circuits a voltage comparator circuit senses if the negative gate voltage is present as an input on pin 1 (gfb) - gate voltage ( - ) feedback. a logic circuit provides the switched input enable signal for the n - channel mosfet. the following 3 signals must be at correct levels to generate the enable logic signal: ? pin 12 (ens) mos switch enable ttl ? negative gate voltage (gfb) is present ? p4v voltage is present.
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 5 5 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 5 applications section part value mfg mfg p/n r1 2.7 k panasonic erj - 2gej272x r2,r3 1.02 k vishay crcw25121k02fkeghp r4,r5 402 vishay crcw2512402rfkeg vr1 10 k bourns 3224w - 1 - 103e q1 p - channel mosfet ir irf5210spbf application option 1: fixed gate with pulsed drain biasing figure 1 shows a block diagram of the mabc - 001000 - dps00l module with the recommended external components to support this application option. see table 1 for component recommendations and values. figure 1. fixed gate/pulsed drain biasing module layout guidelines reference the product view, pin configuration table on page 1, and the recommended landing pattern on page 7. the following recommendations should be followed when the mabc - 001000 - dps00l module is used to bias a high - power rf device or amplifier. the input and output locations were determined so that the layout and signal routing could be optimized when interfacing with a high - power amplifier assembly. ? the negative gate voltage input and outputs are located on the left side of the module and should be located as close as possible to the gate bias pads on the high - power am plif ier assembly. ? the positive pulsed voltages are located on the right side of the module and should be located as close as possible to the external mosfet switch. the mosfet switch drain should be located as close as possible to the drain bias pads on the high - power amplifier assembly. the charge storage capacitors should be located as close as possible to the mosfet switch source terminal pads. ? the module ground pads are located at pins 7, 13, and 14. ? route all signal lines and ground returns to be as short as possible and implement a ground plane on the back of the printed wiring board (pwb) if that option is available to the designer. following these layout criteria will minimize circuit parasitics that degrade the performance of the pulsed signal. table 1. recommended parts list for fixed gate/pulsed drain biasing r f i n r f o u t m a b c - 0 0 1 0 0 0 - d p s 0 0 l d u t + 5 0 v - 8 v t t l 3 9 5 4 6 1 r 1 r 2 v r 1 c o u t c i n r 4 r 3 r 5 c s t o r a g e q 1 + 5 v 1 1
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 6 6 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 6 applications section figure 2. pulsed gate/pulsed drain biasing: (a) north biasing; (b) south biasing figure 3. populated mabc - 001000 - pb2ppr evaluation board figure 4. mabc - 001000 - pb2ppr with mabc - 001000 - dps00l mounted (a) (b) application option 2: pulsed gate and pulsed drain biasing a block diagram showing a typical application of the mabc - 001000 - pb2ppr sample board is shown in figure 2 below. figures 3 and 4 show layouts of the mabc - 001000 - pb2ppr sample board with/without the mabc - 001000 - dps00l module installed. the additional external circuitry on the mabc - 001000 - pb2ppr sam ple board provides the added capability of pulsed gate biasing. it is important to note that the evaluation boards can be configured for either option 1 or 2. a full schematic, assembly layout, and bill of materials are available upon request. typical application circuits single gan device control mabc - 001000 - dps00l +5v 11 multiple gan device control (no rf redundancy) mabc - 001000 - dps00l +5v 11 3 3 mabc-001000-000dpm gan -8vdc 50vdc 2 4 5 6 10 9 8 pwm in out gan in out vpot vtemp dac mabc-001000-000dpm gan vpot vtemp dac -8vdc 50vdc 2 4 5 6 10 9 8 pwm in out r f i n r f o u t m a b c - 0 0 1 0 0 0 - p b 2 p p r d u t + 5 0 v - 8 v t t l v d _ p u l s e d v g _ b v d d t t l - 8 v r f i n r f o u t m a b c - 0 0 1 0 0 0 - p b 2 p p r d u t + 5 0 v - 8 v t t l v d _ p u l s e d v g _ a v d d t t l - 8 v p 4 v p 4 v + 5 v + 5 v
gan bias controller/sequencer module dual supply: - 8 to - 3 v, +5 v rev. v1 mabc - 001000 - dps00l 7 7 m/a - com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: https://www.macom.com/support 7 physical dimensions 10,11,12 recommended landing pattern 7 handling procedures please observe the following precautions to avoid damage: static sensitivity this module is sensitive to electrostatic discharge (esd) and can be damaged by static electricity. proper esd control techniques should be used when handling these hbm class 1b devices. 10. all dimensions are in inches[mm]. 11. reference application note m538 for lead - free solder reflow recommendations. 12. plating is 100% sn over becu.
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